With the improved performance of an information processing apparatus such as a device or a server for communication backbone, the data rate of signal transmission and reception has to increase inside and outside the device. In a transceiver which operates at a high speed, a clock and data recovery (CDR) circuit which recovers an optimal timing clock from a data signal is provided. Multiple architectures have been proposed as a method for realizing the CDR circuit. For example, a method for causing a reference clock to track the phase of received input data is known. In addition, a method is known, in which a phase difference between a recovery clock and input data is detected, and a recovery clock is generated by phase-shifting a reference clock in accordance with the detected phase difference. A timing signal generation circuit detects a phase difference between a recovery clock and input data, and generates a recovery clock by phase-shifting a reference clock in accordance with the detected phase difference.
A timing signal generation circuit performs phase interpolation for synthesizing a recovery clock by weighting multiple reference clocks with phases different from each other. In order to perform phase interpolation with regard to all phases, clocks of four phases, each being shifted by 90 degrees, are used generally. A quadrant of the phase difference is determined by using a detected phase difference between the recovery clock and input data, and weights of clocks of multiple phases which are synthesized according to the phase difference are further determined.
Performing the determination of the quadrant and the weight by means of digital processing has been proposed. Through the digital processing, a control value can be freely set, and it is possible to easily cope with even a change of quadrant, but a rounding error (quantization error) occurs, and phase variation due to code variation at the time of phase tracking caused by the error occurs. In order to reduce the quantization error or the phase variation due to the error, the number of bits of digital data has to be increased, but in this case, there are problems that a circuit size becomes larger, time for digital processing becomes longer, and response speed is decreased.
Non-Patent document 1, “‘A 10-Gb/s CMOS Clock and Data Recovery Circuit With an Analog Phase Interpolator’ Rainer Kreientkamp, et al., IEEE Journal of Solid-State Circuits, Vol. 40, No. 3, pp. 736-743, March 2005” proposes that determination of the quadrant and the weight is realized by analog processing. According to the Non-patent document 1, phase control signals (currents) with four phases corresponding to a phase control digital code are continuously biased at all times, a bias current rate is changed, and a control is performed by interlocking between two phase control of 0 degrees and 180 degrees and two phase control of 90 degrees and 270 degrees. There is a problem that the control is switched near a value in which clocks of phases of 0 degrees and 180 degrees become equal to clocks of phases of 90 degrees and 270 degrees, and thus, phase variation caused by synthesis (interpolation rate) easily occurs.
Japanese Laid-open Patent Publication No. 2001-217682, Japanese Laid-open Patent Publication No. 2003-309543, and Japanese Laid-open Patent Publication No. 2002-123332 are examples of the related art.